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73S8024RN Low Cost Smart Card Interface
DATA SHEET
January 2009 DESCRIPTION
The Teridian 73S8024RN is a single smart card (ICC) interface IC that can be controlled by a dedicated control bus. The 73S8024RN has been designed to provide full electrical compliance with ISO-7816-3, EMV 4.0 (EMV2000) and NDS specifications. Interfacing with the system controller is done through a control bus, composed of digital inputs to control the interface, and one interrupt output to inform the system controller of the card presence and faults. The card clock can be generated by an on-chip oscillator using an external crystal or by connection to a clock signal. The 73S8024RN incorporates an ISO-7816-3 activation/deactivation sequencer that controls the card signals. Level-shifters drive the card signals with the selected card voltage (3V or 5V), coming from an internal Low Drop-Out (LDO) voltage regulator. This LDO regulator is powered by a dedicated power supply input VPC. Digital circuitry is separately powered by a digital power supply VDD. With its embedded LDO regulator, the 73S8024RN is a cost effective solution for any application where a 5V (typically -5% +10%) power supply is available. Hardware support for auxiliary I/O lines, C4 / C8 contacts, is provided*. Emergency card deactivation is initiated upon card extraction or upon any fault generated by the protection circuitry. The fault can be a card over-current, a VDD (digital power supply)**, a VPC (regulator power supply), a VCC (card power supply) or an over-heating fault. The card over-current circuitry is a true current detection function, as opposed to VCC voltage drop detection, as usually implemented in ICC interface ICs. The VDD voltage fault has a threshold voltage that can be adjusted with an external resistor or resistor network. It allows automated card deactivation at a customized VDD voltage threshold value. It can be used, for instance, to match the system controller operating voltage range. *
ADVANTAGES
* Traditional step-up converter is replaced by a LDO regulator: Greatly reduced power dissipation Fewer external components are required Better noise performance High current capability (90mA supplied to the card) SO28 package is pin-to-pin compatible with industry-standard TDA8004 and TDA8024 Card clock STOP (high and low) mode Small format (4x4x0.85mm) 20QFN package option True card over-current detection
* * * *
FEATURES
* Card Interface: Complies with ISO-7816-3, EMV 4.0 and NDS A LDO voltage regulator provides 3V / 5V to the card from an external power supply input Provides at least 90mA to the card ISO-7816-3 Activation / Deactivation sequencer with emergency automated deactivation on card removal or fault detected by the protection circuitry Protection includes 3 voltage supervisors that detect voltage drops on VCC (card), VDD (digital)**, and VPC (regulator) power supplies The VDD voltage supervisor threshold value can be externally adjusted** Over-current detection 150mA max Card clock stop high or low* 2 card detection inputs, 1 for each possible user polarity Auxiliary I/O lines, for C4 / C8 contact signals* Card CLK clock frequency up to 20MHz System Controller Interface: 3 Digital inputs control the card activation / deactivation, card reset and card voltage 4 Digital inputs control the card clock (division rate and card clock stop modes) 1 Digital output, interrupt to the system controller, allows the system controller to monitor the card presence and faults. Crystal oscillator or host clock, up to 27MHz Regulator Power Supply: 4.75V to 5.5V (EMV 4.0) 4.85V to 5.5V (NDS) Digital Interfacing: 2.7V to 5.5V 6kV ESD Protection on the card interface Package: SO28, 20QFN or 32QFN
APPLICATIONS
* * * Set-Top-Box Conditional Access and Pay-perView Point of Sales and Transaction Terminals Control Access and Identification
*
* Pins/functions not available on 20-pin QFN package. ** User VDD_FLT threshold configuration not available on 20-pin QFN package.
* * *
Rev. 1.8
(c) 2009 Teridian Semiconductor Corporation
1
73S8024RN Data Sheet FUNCTIONAL DIAGRAM
VDD 21 [20] {12} VDDF_ADJ 18 [17] NC 5 [2,9,16,25,32] 6 VPC 6 [3] {2}
DS_8024RN_020
VPC FAULT
{13} [21] 22 GND
DIGITAL POWER SUPPLY VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE
VDD FAULT VCC FAULT
ICC FAULT
{10} [18] 19 CMDVCC {11} [19] 20 RSTIN {20} [31] 3 5V/3V {14} [22] 23 OFF {18} [29] 1 CLKDIV1 {19} [30] 2 CLKDIV2 {15} [23] 24 XTALIN {16} [24] 25 XTALOUT [4] 7 CLKSTOP [5] 8 CLKLEV Int_Clk
LDO REGULATOR & VOLTAGE SUPERVISORS
4 [1] {1} GND 14 [12] {6} GND 17 [15] {9} VCC
DIGITAL CIRCUITRY & FAULT LOGIC
R-C OSC.
ICC RESET BUFFER
16 [14] {8} RST
ISO-7816 SEQUENCER XTAL OSC CLOCK GENERATION
ICC CLOCK BUFFER
15 [13] {7} CLK 10 [7] {4} PRES 9 [6] {3} PRES
OVER TEMP
TEMP FAULT
{17} [26] 26 I/OUC [27] AUX1UC 27 [28] AUX2UC 28
11 [8] {5} I/O
ICC I/O BUFFERS
13 [11] AUX1 12 [10] AUX2
Pin numbers reference the 28SO package. [Pin numbers] reference the 32QFN package. {Pin numbers} reference the 20QFN package.
Figure 1: 73S8024RN Block Diagram
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Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
Table of Contents
1 2 3 4 5 6 7 8 9 Pin Description ....................................................................................................................................5 System Controller Interface................................................................................................................7 Power Supply and Voltage Supervision ............................................................................................8 Card Power Supply ..............................................................................................................................9 Over-Temperature Monitor .................................................................................................................9 On-Chip Oscillator and Card Clock ...................................................................................................9 Activation Sequence .........................................................................................................................10 Deactivation Sequence .....................................................................................................................12 OFF and Fault Detection ...................................................................................................................13
10 I/O Circuitry and Timing ....................................................................................................................13 11 Typical Application Schematic.........................................................................................................15 12 Electrical Specification .....................................................................................................................16 12.1Absolute Maximum Ratings .........................................................................................................16 12.2Recommended Operating Conditions .........................................................................................16 12.3Package Thermal Parameters.....................................................................................................16 12.4Smart Card Interface Requirements............................................................................................17 12.5Characteristics: Digital Signals ....................................................................................................19 12.6DC Characteristics.......................................................................................................................20 12.7Voltage / Temperature Fault Detection Circuits ..........................................................................20 13 Mechanical Drawing (20QFN) ...........................................................................................................21 14 Package Pin Designation (20QFN) ...................................................................................................22 15 Mechanical Drawing (32QFN) ...........................................................................................................23 16 Package Pin Designation (32QFN) ...................................................................................................24 17 Mechanical Drawing (SO) .................................................................................................................25 18 Package Pin Designation (SO) .........................................................................................................25 19 Ordering Information .........................................................................................................................26 20 Related Documentation ....................................................................................................................26 21 Contact Information ..........................................................................................................................26 Revision History ........................................................................................................................................27
Rev. 1.8
3
73S8024RN Data Sheet
DS_8024RN_020
Figures
Figure 1: 73S8024RN Block Diagram .......................................................................................................... 2 Figure 2: Activation Sequence - RSTIN Low When CMDVCC Goes Low ................................................ 10 Figure 3: Activation Sequence - RSTIN High When CMDVCCB Goes Low ............................................. 11 Figure 4: Deactivation Sequence ............................................................................................................... 12 Figure 5: Timing Diagram - Management of the Interrupt Line OFF ......................................................... 13 Figure 6: I/O and I/OUC State Diagram...................................................................................................... 14 Figure 7: I/O - I/OUC Delays Timing Diagram ........................................................................................... 14 Figure 8: 73S8024RN - Typical Application Schematic ............................................................................. 15 Figure 9: 20QFN Mechanical Drawing ....................................................................................................... 21 Figure 10: 20QFN Pin Out .......................................................................................................................... 22 Figure 11: 32QFN Mechanical Drawing ..................................................................................................... 23 Figure 12: 32QFN Pin Out .......................................................................................................................... 24
Tables
Table 1: Choice of VCC Pin Capacitor ........................................................................................................... 9 Table 2: Card Clock Frequency .................................................................................................................... 9
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DS_8024RN_020
73S8024RN Data Sheet
1
Pin Description
Pin 28SO 11 13 12 16 15 Pin 20QFN 5 - - 8 7 Pin Description 32QFN 8 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. 14 Card reset: provides reset (RST) signal to card. 13 Card clock: provides clock signal (CLK) to card. The rate of this clock is determined by the external crystal frequency or frequency of the external clock signal applied on XTALIN and CLKDIV selections. 7 Card Presence switch: active high indicates card is present. Should be tied to GND when not used, but it Includes a high-impedance pull-down current source. 6 Card Presence switch: active low indicates card is present. Should be tied to VDD when not used, but it Includes a high-impedance pull-up current source. 15 Card power supply - logically controlled by sequencer, output of LDO regulator. Requires an external filter capacitor to the card GND. 12 Card ground.
CARD INTERFACE Name I/O AUX1 AUX2 RST CLK
PRES
10
4
PRES
9
3
VCC
17
9
GND
14
6
MISCELLANEOUS INPUTS AND OUTPUTS Name XTALIN XTALOUT VDDF_ADJ Pin 28SO 24 25 18 Pin 20QFN 15 16 - Pin 32QFN 23 24 17 Description Crystal oscillator input: can either be connected to crystal or driven as a source for the card clock. Crystal oscillator output: connected to crystal. Left open if XTALIN is being used as external clock input. VDD fault threshold adjustment input: this pin can be used to adjust the VDDF values (that controls deactivation of the card). Must be left open if unused. Non-connected pin.
NC
5
-
2, 9, 16, 25, 32
POWER SUPPLY AND GROUND Name VDD VPC GND GND Pin 28SO 21 6 4 22 Pin 20QFN 12 2 1 13 Pin 32QFN 20 3 1 21 Description System interface supply voltage and supply voltage for internal circuitry. LDO regulator power supply source. LDO Regulator ground. Digital ground.
Rev. 1.8
5
73S8024RN Data Sheet MICROCONTROLLER INTERFACE Name CMDVCC Pin 28SO 19 Pin 20QFN 10
DS_8024RN_020
5V/#V
3
20
CLKSTOP
7
-
CLKLVL
8
-
CLKDIV1 CLKDIV2
1 2
18 19
Pin Description 32QFN 18 Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, if a card is present. 31 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low selects 3 volt operation. When the part is to be used with a single card voltage, this pin should be tied to either GND or VDD. However, it includes a high impedance pull-up resistor to default this pin high (selection of 5V card) when not connected. 4 Stops the card clock signal during a card session when set high (card clock STOP mode). Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used. 5 Sets the logic level of the card clock STOP mode when the clock is de-activated by setting pin 7 high. Logic low selects card STOP low. Logic high selects card STOP high. Internal pull-down resistor allows this pin to be left as an open circuit if the clock STOP mode is not used. 29 Sets the divide ratio from the XTAL oscillator (or external 30 clock input) to the card clock. These pins include pull-down resistors. CLKDIV1 CLKDIV2 CLOCK RATE 0 0 XTALIN/8 0 1 XTALIN/4 1 1 XTALIN/2 1 0 XTALIN Interrupt signal to the processor. Active Low - Multifunction indicating fault conditions and card presence. Open drain output configuration. It includes an internal 21k pull-up to VDD. Reset Input: This signal is the reset command to the card. System controller data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD. System controller auxiliary data I/O to/from the card. Includes a pull-up resistor to VDD.
OFF
23
14
22
RSTIN I/OUC AUX1UC AUX2UC
20 26 27 28
11 17 - -
19 26 27 28
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73S8024RN Data Sheet
2 System Controller Interface
Three separated digital inputs allow direct control of the card interface from the host as follows: * * * Pin CMDVCC: When low, starts an activation sequence. Pin RSTIN: controls the card Reset signal (when enabled by the sequencer). Pin 5V/#V: Defines the card voltage.
Card clock is controlled by four digital inputs: * * * CLKDIV1 and CLKDIV2 define the division rate for the clock frequency, from the input clock frequency (crystal or external clock). CLKSTOP (active high) allows card power down mode by stopping the card clock. CLKLEV defines the card clock level of the card power down mode.
Interrupt output to the host: As long as the card is not activated, the OFF pin informs the host about the card presence only (Low = No card in the reader). When CMDVCC is set low (Card activation sequence requested from the host), low level on OFF means a fault has been detected (e.g. card removal during card session, or voltage fault, or thermal / over-current fault) that automatically initiates a deactivation sequence.
Rev. 1.8
7
73S8024RN Data Sheet
DS_8024RN_020
3 Power Supply and Voltage Supervision
The 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller. Three voltage supervisors constantly check the presence of the voltages VDD, VPC and VCC. A card deactivation sequence is forced upon fault of any of these voltage supervisors. The two voltage supervisors for VPC and VCC are linked so that a fault is generated to activate a deactivation sequence when the voltage VPC becomes lower than VCC. It allows the 73S8024RN to operate at lower VPC voltage when using 3V cards only. The voltage regulator can provide a current of at least 90mA on VCC that comply easily with EMV 4.0 and NDS specifications. The VPC voltage supervisor threshold values are defined from applicable standards (EMV and NDS). A third voltage supervisor monitors the VDD voltage. It is used to initialize the ISO-7816-3 sequencer at power-on, and to deactivate the card at power-off or upon fault. The voltage threshold of the VDD voltage supervisor is internally set by default to 2.3V nominal. However, it may be desirable, in some applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the 32QFN package, not supported in the 20QFN package) is used to connect an external resistor REXT to ground to raise the VDD fault voltage to another value VDDF. The resistor value is defined as follows: REXT= 56k /(VDDF - 2.33) An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from the pin to supply and R1 from the pin to ground (see applications diagram). In order to set the new threshold voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is defined as R1/(R1+R3). Kx is calculated as: Kx = (2.789 / VTH) - 0.6125 where VTH is the desired new threshold voltage. To determine the values of R1 and R3, use the following formulas. R3 = 24000 / Kx R1 = R3*(Kx / (1 - Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives: Kx = (2.789 / 2.7) - 0.6125 = 0.42046. Solving for R3 gives: R3 = 24000 / 0.42046 = 57080. Solving for R1 gives: R1 = 57080 *(0.42046 / (1 - 0.42046)) = 41412. Using standard 1 % resistor values gives R3 = 57.6K and R1 = 42.4K. These values give an equivalent resistance of Kx = 0.4228, a 0.6% error. If the 2.3V default threshold is used, this pin must be left unconnected. The 20QFN package has the VDD fault threshold fixed at this default value.
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73S8024RN Data Sheet
4 Card Power Supply
The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO-7816-3 sequencer. Card voltage selection is carried out by the digital input 5V/#V. Choice of the VCC Capacitor: Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card are different. An external capacitor must be connected between the VCC pin and to the card ground in order to guarantee stability of the LDO regulator, and to handle the transient requirements. The type and value of this capacitor can be optimized to meet the desired specification. Table 1 shows the recommended capacitors for each VPC power supply configuration and applicable specification. Table 1: Choice of VCC Pin Capacitor Specification Requirements Specification EMV 4.0 ISO-7816-3 NDS Min VCC Voltage Allowed During Transient Current 4.6V 4.5V 4.6V Max Transient Current Charge 30nA.s 20nA.s 40nA.s Min VPC Power Supply Required 4.75V 4.75V 4.85V System Requirements Capacitor Type X5R/X7R w/ ESR < 100m Capacitor Value 3.3 F 1 F 1 F
Note: Capacitor value for NDS implementation is also defined by the deactivation time requirement.
5 Over-Temperature Monitor
A built-in detector monitors die temperature. Upon an over-temperature condition, a card deactivation sequence is initiated, and an error or fault condition is reported to the system controller.
6 On-Chip Oscillator and Card Clock
The 73S8024RN device has an on-chip oscillator that can generate the smart card clock using an external crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the clock signal is available from another source, it can be connected to the pin XTALIN, and the pin XTALOUT should be left unconnected. The card clock frequency may be chosen between four different division rates, defined by digital inputs CLKDIV 1 and CLKDIV 2, as per Table 2. Table 2: Card Clock Frequency CLKDIV1 0 0 1 1 CLKDIV2 0 1 0 1 CLK XTALIN 1/4 XTALIN XTALIN 1/2 XTALIN
Card power down mode (card clock STOP) is supported and is controllable through the dedicated digital inputs CLKSTOP and CLKLEV (not supported in the 20QFN package).
Rev. 1.8
9
73S8024RN Data Sheet
DS_8024RN_020
7 Activation Sequence
The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no over-temperature fault or no VDD fault. The following steps show the activation sequence and the timing of the card control signals when the system controller sets CMDVCC low while the RSTIN is low: * * CMDVCC is set low. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during t1. If VCC does not become valid, the OFF goes low to report a fault to the system controller, and the power VCC to the card is shut off. Turn I/O (AUX1, AUX2) to reception mode at the end of (t2). CLK is applied to the card at the end of (t3). RST is a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not set RST high until 42000 clock cycles after the start of CLK.
* * *
CMDVCC VCC I/O CLK RSTIN RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator) t2 = 1.5s, I/O goes to reception state t3 = >0.5s, CLK starts t4 42000 card clock cycles. Time for RST to become the copy of RSTIN Figure 2: Activation Sequence - RSTIN Low When CMDVCC Goes Low
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73S8024RN Data Sheet
The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: * * CMDVCC is set low. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the system controller, and the power VCC to the card is shut down. Due to the fall of RSTIN at (t2), turn I/O (AUX1, AUX2) to reception mode. CLK is applied to the card at the end of (t3), after I/O is in reception mode. RST is to be a copy of RSTIN after (t4). RSTIN may be set high before t4, however the sequencer will not set RST high until 42000 clock cycles after the start of CLK.
* * *
CMDVCC VCC I/O CLK RSTIN RST
t1
t2
t3
t4
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator) t2 = 1.5s, I/O goes to reception state t3 = > 0.5s, CLK active t4 42000 card clock cycles. Time for RST to become the copy of RSTIN Figure 3: Activation Sequence - RSTIN High When CMDVCCB Goes Low
Rev. 1.8
11
73S8024RN Data Sheet
DS_8024RN_020
8 Deactivation Sequence
Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated when VPC goes lower than VCC. The following steps show the deactivation sequence and the timing of the card control signals when the system controller sets the CMDVCC high or OFF goes low due to a fault or card removal: * * * * RST goes low at the end of t1. CLK is set low at the end of t2. I/O goes low at the end of t3. Out of reception mode. VCC is shut down at the end of time t4. After a delay t5 (discharge of the VCC capacitor), VCC is low.
CMDVCC OFF
-- OR --
RST CLK I/O VCC
t1
t2
t3
t4
t5
t1 = t2 = t3 = t4 = t5 =
> 0.5s, timing by 1.5MHz internal Oscillator > 7.5s > 0.5s > 0.5s depends on VCC filter capacitor. For NDS application, CF=1F makes t1 + t2 + t3 + t4 + t5 < 100s Figure 4: Deactivation Sequence
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73S8024RN Data Sheet
9 OFF and Fault Detection
There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal. No deactivation is required during this time. During a card session: CMDVCC is always low, and OFF falls low if the card is extracted or if any fault detection is detected. At the same time that OFF is set low, the sequencer starts the deactivation process. The Figure 5 shows the timing diagram for the signals CMDVCC, PRES, and OFF during a card session and outside the card session: rd
OFF is low by card extracted
PRES OFF CMDVCC VCC
OFF is low by any fault
outside card session
within card session
within card session
Figure 5: Timing Diagram - Management of the Interrupt Line OFF
10 I/O Circuitry and Timing
The states of the I/O, AUX1, and AUX2 pins are low after power on reset and they are in high when the activation sequencer turns on the I/O reception state. See the Activation Sequence section for more details on when the I/O reception is enabled. The states of I/OUC, AUX1UC, and AUX2UC are high after power on reset. Within a card session and when the I/O reception state is turn on, the first I/O line on which a falling edge is detected becomes the input I/O line and the other becomes the output I/O line. When the input I/O line rising edge is detected then both I/O lines return to their neutral state. Figure 6 shows the state diagram of how the I/O and I/OUC lines are managed to become input or output. The delay between the I/O signals is shown in Figure 7.
Rev. 1.8
13
73S8024RN Data Sheet
DS_8024RN_020
Neutral State
No
I/O reception
Yes I/O & not I/OUC No Yes No I/OUC & not I/O Yes I/OUC in No I/OUC yes I/O yes I/OICC in No
Figure 6: I/O and I/OUC State Diagram
I/O
I/OUC
tI/O_HL
Delay from I/O to I/OUC: Delay from I/OUC to I/O:
tI/O_LH
tI/O_HL = 100ns tI/OUC_HL = 100ns
tI/OUC_HL
tI/OUC_LH
tI/O_LH = 25ns tI/OUC_LH = 25ns
Figure 7: I/O - I/OUC Delays Timing Diagram
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73S8024RN Data Sheet
11 Typical Application Schematic
AUX2UC_to/from_uC AUX1UC_to.from_uC VDD See NOTE 6 See NOTE 3 I/OUC_to/from_uC See NOTE 5
CLKDIV1_from_uC CLKDIV2_from_uC 5V/3V_select_from_uC
VDD - OR C4 100nF C5 10uF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLKDIV1 CLKDIV2 5V3V_ GND NC VPC CLKSTOP CLKLVL PRESB PRES I/O AUX2 AUX1 GND AUX2UC AUX1UC I/OUC XTALOUT XTALIN OFF_ GND VDD RSTIN CMDVCC_ VDDF_ADJ VCC RST CLK 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R3 Rext2
External_clock_from uC
VPC See NOTE 2
C2 22pF C3 22pF
VDD See NOTE 1 C6 100nF R1 Rext1
Y1 CRYSTAL
CLKSTOP_from_uC CLKLVL_from_uC See NOTE 5
See NOTE 4
73S8024RN
SO28
See note 7 OFF_interrupt_to_uC RSTIN_from_uC
VDD R2 NOTES: Card detection 1) VDD = 2.7V to 5.5V DC. 20K switch is normally closed 2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC 3) Required if external clock from uP is used. 4) Required if crystal is used. Y1, C2 and C3 must be removed if external clock is used. 5) Optional. Can be left open. 6)Internal pull-up allows it to be left open if unused. 7) R1 and R3 are external resistors that adjust the VDD fault voltage. Can be left open. NDS & ISO7816=1uF, EMV=3.3uF Low ESR (<100mohms) C1 C1 should be placed near the SC connecter contact C8 I/O VPP GND C4 CLK RST VCC 8 7 6 5 4 3 2 1
CMDVCC_from_uC
SW-2 SW-1
10 9
CLK track should be routed far from RST, I/O, C4 and C8.
Smart Card Connector
Figure 8: 73S8024RN - Typical Application Schematic
Rev. 1.8
15
73S8024RN Data Sheet
DS_8024RN_020
12 Electrical Specification
12.1 Absolute Maximum Ratings
Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Parameter Supply Voltage VDD Supply Voltage VPC Input Voltage for Digital Inputs Storage Temperature Pin Voltage (except card interface) Pin Voltage (card interface) ESD Tolerance - Card interface pins ESD Tolerance - Other pins Rating -0.5 to 6.0 VDC -0.5 to 6.0 VDC -0.3 to (VDD +0.5) VDC -60 to 150C -0.3 to (VDD +0.5) VDC -0.3 to (VCC + 0.5) VDC +/- 6kV +/- 2kV
*Note: ESD testing on smart card pins is HBM condition, 3 pulses, each polarity referenced to ground. Note: Smart Card pins are protected against shorts between any combinations of Smart Card pins.
12.2 Recommended Operating Conditions
Parameter Supply Voltage VDD Supply Voltage VPC NDS Supply Voltage VPC Ambient Operating Temperature Input Voltage for Digital Inputs Rating 2.7 to 5.5 VDC 4.75 to 5.5 VDC 4.85 to 5.5 VDC -40C to +85C 0V to VDD + 0.3V
12.3 Package Thermal Parameters
Package 28 SO 32QFN 32QFN 20QFN 20QFN Rating 44 C / W 47 C / W (with bottom pad soldered) 78 C / W (without bottom pad soldered) 53 C / W (with the bottom pad soldered) 90 C / W (without the bottom pad soldered)
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73S8024RN Data Sheet
12.4 Smart Card Interface Requirements
Symbol Parameter Condition Min Typ Max Unit Card Power Supply (VCC) Regulator General conditions, -40C < T < 85C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v NDS conditions, 4.85v < VPC < 5.5v Inactive mode Inactive mode ICC = 1mA Active mode; ICC <65mA; 5v Active mode; ICC <65mA; 5v, NDS condition Active mode; ICC <90mA; 5v Active mode; ICC <90mA; 3v Active mode; single pulse of 100mA for 2s; 5 volt, fixed load = 25mA Active mode; single pulse of 100mA for 2s; 3v, fixed load = 25mA Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5v Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 5v, NDS condition Active mode; current pulses of 40nAs with peak |ICC | <200mA, t <400ns; 3v fRIPPLE = 20K - 200MHz Static load current, VCC>4.6 Static load current, VCC>4.55 or 2.7 volts as selected CF = 3.3F on VCC CF = 1.0F on VCC NDS applications
CF should be ceramic with low ESR (<100m).
-0.1 -0.1 4.60 4.75 4.55 2.80 4.6
0.1 0.4 5.25 5.25 5.25 3.2 5.25
V V V V V V V
VCC
Card supply voltage including ripple and noise
2.76
3.2
V
4.6
5.25
V
4.65
5.25
V
2.76
3.2 350
V mV mA mA
VCCrip ICCmax ICCF VSR - VSF VSRN VSFN CF CFNDS
VCC Ripple Card supply output current ICC fault current VCC slew rate VCC slew rate External filter capacitor (VCC to GND) External filter capacitor (VCC to GND)
65 90 90 0.02 0.06 1 0.5 0.050 0.160 3.3 1.0 150 0.08 0.26 5 1.5
mA
V/s V/s
F F
NDS applications
CF should be ceramic with low ESR (<100m).
Rev. 1.8
17
73S8024RN Data Sheet
DS_8024RN_020
Symbol
Parameter
Condition
Min
Typ
Max
Unit
Interface Requirements - Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC. VOH VOH VOL VIH VIH VIL VINACT ILEAK IIL ISHORTL ISHORTH Output level, high (I/O, AUX1, AUX2) Output level, high (I/OUC, AUX1UC, AUX2UC) Output level, low Input level, high (I/O, AUX1, AUX2) Input level, high (I/OUC, AUX1UC, AUX2UC) Input level, low Output voltage when outside of session Input leakage Input current, low Short circuit output current IOH =0 IOH = -40A IOH =0 IOH = -40A IOL=1mA 0.9 VCC 0.75 VCC 0.9 VDD 0.75 VDD 1.8 1.8 -0.3 IOL = 0 IOL = 1mA VIH = VCC VIL = 0 For output low, shorted to VCC through 33 ohms For output high, shorted to ground through 33 ohms For I/O, AUX1, AUX2, CL = 80pF, 10% to 90%. For I/OUC, AUX1UC, AUX2UC, CL=50Pf, 10% to 90%. Output stable for >200ns 8 60 Edge from master to slave, measured at 50% 11 100 VCC+0.1 VCC+0.1 VDD+0.1 VDD+0.1 0.3
VCC+0.30 VDD +0.30
V V V V V V V V V V A mA mA
0.8 0.1 0.3 10 0.65 15
Short circuit output current
15
mA
tR, tF
Output rise time, fall times
100
ns
tIR, tIF RPU FDMAX TFDIO
Input rise, fall times Internal pull-up resistor Maximum data rate Delay, I/O to I/OUC, AUX1 to AUX1UC, AUX2 to AUX2UC, I/OUC to I/O, AUX1UC to AUX1, AUX2UC to AUX2 (respectively falling edge to falling edge and rising edge to rising edge) Input capacitance
1 14 1 200
s k
MHz
ns
TRDIO
25
90
ns
CIN
10
pF
18
Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
Symbol VOH VOL VINACT IRST_LIM ICLK_LIM CLKSR3V CLKSR5V tR, tF
Parameter Output level, high Output level, low Output voltage when outside of session Output current limit, RST Output current limit, CLK CLK slew rate CLK slew rate Output rise time, fall time
Condition IOH =-200A IOL=200A IOL = 0 IOL = 1mA
Min 0.9 VCC 0
Typ
Max VCC 0.3 0.1 0.3 30 70
Unit V V V V mA mA V/ns V/ns ns ns %
Reset and Clock for card interface, RST, CLK
Duty cycle for CLK
Vcc = 3V Vcc = 5V CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35Pf, FCLK 20MHz
0.3 0.5 8 100 45 55
12.5 Characteristics: Digital Signals
Symbol VIL VIH VOL VOH ROUT |IIL1| VILXTAL VIHXTAL IILXTAL fMAX Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Pull-up resistor, OFF Input Leakage Current Input Low Voltage - XTALIN Input High Voltage - XTALIN Input Current XTALIN Max freq. Osc or external clock External input duty cycle limit GND < VIN < VDD Condition Min -0.3 0.7 VDD IOL = 2mA IOH = -1mA VDD - 0.45 16 -5 -0.3 0.7 VDD GND < VIN < VDD -30 21 24 5 0.3 VDD VDD+0.3 30 27 tR/F < 10% fIN, 45% < CLK < 55% 48 52 Typ Max 0.8 VDD + 0.3 0.45 Unit V V V V k A V V A MHz %
Digital I/O Except for OSC I/O
Oscillator (XTALIN) I/O Parameters
in
Rev. 1.8
19
73S8024RN Data Sheet
DS_8024RN_020
12.6 DC Characteristics
Symbol IDD IPC Parameter Supply Current Supply Current VPC supply current when VCC = 0 VCC on, ICC=0 I/O, AUX1, AUX2=high, Clock not toggling CMDVCC High Condition Min Typ 2.7 450 Max 7.0 650 Unit mA A
IPCOFF
345
550
A
12.7 Voltage / Temperature Fault Detection Circuits
Symbol VDDF VPCF VCCF TF Parameter VDD fault (VDD Voltage supervisor threshold) VPC fault (VPC Voltage supervisor threshold) VCC fault (VCC Voltage supervisor threshold) Die over temperature fault Condition No external resistor on VDDF_ADJ pin VPCVCC - 0.2 4.55 2.7 145
V V V C
20
Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
13 Mechanical Drawing (20QFN)
0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 4.0
20
0.20 REF 2.0
1 2
4.0
2.0 SEATING PLANE
TOP VIEW
0.18 / 0.30 2.50 / 2.70 1.25 / 1.35
SIDE VIEW
0.20 MIN 0.18 / 0.30
2.50 / 2.70
2 1
K
1.25 / 1.35
0.35 / 0.45 20 19 0.50 0.20 MIN
PIN #1 ID R 0.20
BOTTOM VIEW
Figure 9: 20QFN Mechanical Drawing
Rev. 1.8
21
73S8024RN Data Sheet
DS_8024RN_020
CAUTION: Use handling procedures necessary for a static sensitive component
14 Package Pin Designation (20QFN)
19 CLKDIV2
20
18
17
GND VPC PRES PRES I/O
1 2 3 4 5 7 8 6 9 CLK RST GND VCC
16 15 14
XTALOUT
CLKDIV1
5V/#V
I/OUC
XTALIN OFF GND VDD RSTIN
TERIDIAN 8024RN
10 CMDVCC
13 12 11
Figure 10: 20QFN Pin Out
22
Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
15 Mechanical Drawing (32QFN)
0 .8 5 N O M ./ 0 .9 M A X . 0 .0 0 / 0 .0 0 5
5 2.5
0 .2 0 R E F .
1 2 3
2.5 5
S E A T IN G PLANE
TOP VIEW
S ID E V IE W
0.35 / 0.45
3.0 / 3.75 0.18 / 0.3 1.5 / 1.875
CHAMFERED 0.30
1 2 3 3.0 / 3.75 0.25 1.5 / 1.875 0.2 MIN. 0.35 / 0.45
Figure 11: 32QFN Mechanical Drawing
0.5 0.5 0.25
BOTTOM VIEW
Rev. 1.8
23
73S8024RN Data Sheet
DS_8024RN_020
CAUTION: Use handling procedures necessary for a static sensitive component
16 Package Pin Designation (32QFN)
CLKDIV2
CLKDIV1
AUX2UC
AUX1UC
5V/#V
I/OUC 26
NC
32
31
30
29
28
27
GND NC VPC CLKSTOP CLKLVL PRES PRES I/O
1 2 3 4 5 6 7 8 10 11 12 13 14 15 AUX1 AUX2 CLK NC RST GND VCC NC 16 9
25 24 23 22
NC
XTALOUT XTALIN OFF GND VDD RSTIN CMDVCC VDDF_ADJ
TERIDIAN S8024RN
21 20 19 18 17
Figure 12: 32QFN Pin Out
24
Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
17 Mechanical Drawing (SO)
.050 TYP. (1.270)
.305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .0115 (0.29) .003 (0.076)
.420 (10.668) .390 (9.906)
.110 (2.790) .092 (2.336) .016 nom (0.40)
.335 (8.509) .320 (8.128)
Figure 13: 28 Lead SO
18 Package Pin Designation (SO)
(Top View)
CLKDIV1 CLKDIV2 5V3V GND NC VPC CLKSTOP CLKLVL PRES PRES I/O AUX2 AUX1 GND
1 2 3 4 5 28 27 26 25 24
CAUTION: Use handling procedures necessary for a static sensitive component
AUX2UC AUX1UC I/OUC XTALOUT XTALIN OFF GND VDD RSTIN CMDVCC
VDDF_ADJ
6 7 8 9 10 11 12 13 14
TERIDIAN 73S8024RN
23 22 21 20 19 18 17 16 15
VCC RST CLK
Figure 14: 28SO 73S8024RN Pin Out
Rev. 1.8
25
73S8024RN Data Sheet
DS_8024RN_020
19 Ordering Information
Part Description 73S8024RN-SOL 28-pin Lead-Free SO 73S8024RN-SOL 28-pin Lead-Free SO Tape / Reel 73S8024RN-32QFN 32-pin Lead-Free QFN 73S8024RN-32QFN 32-pin Lead-Free QFN Tape / Reel 73S8024RN-20QFN 20-pin Lead-Free QFN 73S8024RN-20QFN 20-pin Lead-Free QFN Tape / Reel Order No. 73S8024RN-IL/F 73S8024RN-ILR/F 73S8024RN-32IM/F 73S8024RN-32IMR/F 73S8024RN-20IM/F 73S8024RN-20IMR/F Packaging Mark 73S8024RN-IL 73S8024RN-IL S8024RN S8024RN 8024RN 8024RN
20 Related Documentation
The following 73S8024RN documents are available from Teridian Semiconductor Corporation: 73S8024RN Data Sheet (this document) 73S8024RN Combination 28SO/20QFN Demo Board User Guide 73S8024RN 28SO Demo Board User's Guide Achieving EMV Electrical Compliance with the TERIDIAN 73S8024RN Dual Footprint Layout 73S8024RN vs NXP TDA8024T Implementing the TERIDIAN 73S8024RN in NDS Applications
21 Contact Information
For more information about Teridian Semiconductor products or to check the availability of the 73S8024RN, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 Telephone: (714) 508-8800 FAX: (714) 508-8878 Email: scr.support@teridian.com For a complete list of worldwide sales offices, go to http://www.teridian.com.
26
Rev. 1.8
DS_8024RN_020
73S8024RN Data Sheet
Revision History
Revision 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Date 5/18/2004 11/5/2004 4/27/2005 7/15/2005 8/23/2005 12/5/2007 1/17/2008 1/19/2009 Removes leaded package options, replaces 32QFN punched with SAWN mechanical dimensions, update 28SO package dimensions. Changed dimension of bottom exposed pad on 32QFN mechanical package figure. In Figure 1, modified the device block diagram to make pin 2 a no connect. Also, changed the pin description. In Figure 9, changed the mechanical drawing for the 20QFN package. Added the NDS logo to page 1 and assigned document number. Added the Related Documentation and the Contact Information sections. Added 20QFN package option and ordering information. Updated 32 QFN ordering information. Description First publication.
(c) 2009 Teridian Semiconductor Corporation. All rights reserved. Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation. All other trademarks are the property of their respective owners. Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company's warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on http://www.teridian.com or by checking with your sales representative. Teridian Semiconductor Corp., 6440 Oak Canyon Rd., Suite 100, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.Teridian.com Rev. 1.8 27

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